SoC Physical Design Engineer

We Are

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow.

You Are

You are a highly experienced SoC Physical Design Engineer, responsible for leading physical design implementation projects for complex, highspeed SoCs, working closely with local and remote teams and customers. The role focuses on delivering endtoend RTLtoGDSII execution for full SoCs and industrystandard IP subsystems and Chiplets.

You have deep, handson expertise in SoC physical design, static timing analysis, and physical signoff, combined with practical experience implementing highspeed interface IP subsystems such as PCIe, CXL, USB, DisplayPort, Ethernet, and DDR. You bring a strong understanding of interface standards, subsystem integration requirements, clocking architectures, power management techniques, and signal integrity considerations, enabling you to drive robust and scalable implementations for complex SoC designs using Synopsys EDA Tools and IPs.

You will work closely with frontend, IP, methodology, backend teams, and customers to drive timing closure, PPA optimization, and successful tapeouts, while providing strong technical leadership and ensuring highquality execution using Synopsys tools and RTLtoGDSII methodologies.

What You'll Be Doing

• Lead physical design projects for complex, high-speed SOCs, IP Subsystems and Chiplets, working with local and remote teams.
• Take full ownership of the RTL-to-GDSII implementation flow, including synthesis, floor planning, partitioning, DFT, UPF-based low power design, CTS, routing, extraction, and signoff
• Develop and debug timing constraints, drive static timing analysis (STA), and resolve timing and PPA bottlenecks and provide structural design changes achieve the PPA goals
• Collaborate closely with front-end teams to optimize data path, clock and reset architecture for high-speed timing closure
• Own the creation, qualification, and maintenance of block and SOC-level constraints, including timing ECOs and signoff
• Work on physical verification tasks (DRC, LVS, IR/EM analysis) and power/IR drop signoff, ensuring robust handoff to manufacturing
• Automate and enhance implementation flows with scripting (Python, TCL, PERL) and maintain design data integrity using GIT and Perforce
• Strong knowledge of AIbased development solutions and productivity tools, including GitHub and Cursor, to accelerate engineering workflows.
• Act as a technical mentor and point of escalation for cross-functional teams, providing hands-on support and guidance on methodology and tool usage

The Impact You Will Have

• Deliver production-grade SOCs that meet aggressive PPA targets and tight schedules for Synopsys customers worldwide
• Drive adoption and customization of Synopsys R2G flows to meet unique customer needs, improving delivery efficiency
• Identify and resolve critical implementation bottlenecks, directly reducing project risk and increasing the likelihood of first-pass silicon success
• Set the technical standard for physical design excellence in the System Solution Group, raising the bar for both process and results
• Mentor engineers across multiple geographies, building capability and confidence in the next wave of SOC design leads
• Serve as the trusted technical liaison for customer-facing engagements, strengthening Synopsys' reputation as a solutions partner

What You'll Need

• MS in Electrical Engineering (or equivalent) and 10+ years hands-on experience in SOC physical design and static timing analysis
• Expert-level proficiency with Synopsys RTL-to-GDSII tools (Fusion Compiler, PrimeTime, PrimeClosure, TCM, RTLA, Formality, VC Spyglass, StarRCXT, ICV)
• Demonstrated leadership in managing and mentoring both local and remote implementation teams on complex, high-speed digital and mixed-signal SOCs
• Deep hands-on experience across the full backend flow: synthesis, floorplanning, partitioning, DFT, low power/UPF, CTS, routing, extraction, timing and signoff, physical verification, and power/IR drop analysis
• Strong scripting skills in Python, TCL, and PERL, with experience using GIT and Perforce for design data management
• Experience with low power design techniques including multi-supply, shutdown, and DVFS, and UPF constraint development
• Ability to travel and occasionally work on-site at customer premises as needed
• Experience working in a customer-focused environment; strong communication and presentation skills are a plus
• Fluent and confident in English; fluency in German is preferred.

Who You Are

• You turn ambiguous requirements into concrete plans, asking the right questions and pushing for clarity without slowing things down
• You consistently identify timing and PPA risks early and lead structured rootcause analysis to ensure robust, longterm solutions.
• You explain technical tradeoffs to both engineers and customers in language that lands, never losing the nuance or the bigger picture
• You bring calm and focus to high-pressure tapeout milestones, leading by example and keeping the team moving forward
• You're always looking for a better way-whether that's automating a tedious task, improving a flow, or sharing hard-won lessons with the team
  

The Team You'll Be Part Of

You'll join the System Solution Group at Synopsys, a customerfacing expert engineering organization that delivers architecture, RTL, verification, and implementation services, often endtoend, to help customers successfully tape out the most complex SoCs using Synopsys tools and IP.

You'll collaborate with experts across continents, combining deep technical knowledge with practical delivery, and play a central role in shaping the next generation of silicon products.

Rewards and Benefits

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings.

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.