STA Engineer (M, F, D)

We are looking for talented engineers to join our STA team. In this role, you will be working closely with multiple integration teams, like DFT, Top Level PNR, PHY designers and PNR teams.

You will be responsible for:\nDeveloping automated block and full chip level signoff flows\nFull Chip Timing/Noise convergence and full signoff for high quality TO\nEnabling hierarchical Timing flows\nPower optimizations\nGenerating block level budget and context for correlation with Full Chip\nDriving custom IP integration and custom timing checks flows\nClosing work with Design, DFT, architecture and Power team

You hold a MSEE or equivalent strong experience in Static Timing analysis\nExtensive experience with one of the commercial STA tools\nAbility to fluently speak and write in English.

Familiarity with hierarchical design approach, top-down design, timing and physical convergence\nExperience with backend STA closure and Signoff\nDeep understanding of designs' constraints development\nGood understanding of AC timing from specs to implementation\nGood understanding of DFT modes and their constraints\nGood communication skills and team player\nQuick learning of flows and methods\nAdvantage - Understanding noise and signal integrity effects\nAdvantage - Timing margins fundamental from synthesis to signoff\nAdvantage - Experience with scripting