SoC Physical Design Verification Engineer (M, F, D)

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Joining this group means you'll be crafting and building the technology that fuels Apple's devices. Together, we enable our customers to do all the things they love with their devices. In this highly visible role, you will be a critical part of a growing team responsible for physical verification of SOC's in Munich, Germany. Join us!

Work with Physical Design team to understand chip architecture and drive physical verification aspects early in design cycle.

Graduate in MSEE.\nAbility to fluently speak and write in English.

Familiar with hierarchical design approach, top-down design.\nExperience with padring, bump, RDL design.\nFamiliar with GDS assembly, GDS requirements for hard macros.\nAnalog/Digital Layout design background and experience is a plus.\nExperienced in industry standard tools used for physical verification such as Mentor Calibre as well as collaborating with foundries.\nFamiliar with TCL scripting.